1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Description of the Related Art
The full-silicide (FUSI) technologies in which a gate electrode is fully silicided have been reported by various research institutes as a promising technology for suppressing the gate depletion that has come to be conspicuous in the very thin gate insulator films of the 90 nm node and latter nodes.
Among other full-silicide technologies, a full-silicide gate structure using nickel is deemed to be promising, in view of simplicity of process and ease of production of a thin film silicide. In relation to the nickel full-silicide gate, a structure has been reported in which the respective nickel and silicon contents in an N-type FET and a P-type FET are varied for the purpose of optimizing the respective gate electrode work functions for the N-type FET and the P-type FET (refer to, for example, Dual Workfunction NiSilicide/HfSiON Gate Stacks by Phase-controlled Full-Silicidation (PC FUSI) Technique for 45 nm-node LSTP and LOP Devices (K. Takahashi, 2004, IEDM, p. 91), hereinafter referred to as Non-Patent Document 1). A compositional ratio (content ratio) ensuring that the N-type FET gate electrode is of an NiSi2 structure and the P-type FET gate electrode is of an Ni3Si type is desirable from the viewpoint of work function.
It has been reported, however, that in the case of forming an Ni3Si type full-silicide gate structure, the volume expansion in the process of reaction between nickel and silicon is excessively large, and the load of the resultant stress causes the problem that nickel oozes from gate ends into the channel region (refer to, for example, Strain Controlled CMOSFET with Phase Controlled Full-Silicide (PC-FUSI)/HfSiON Gate Stack Structure for 45 nm-node LSTP Devices (M. Saitoh, 2006 Symp. On VLSI tech.), hereinafter referred to as Non-Patent Document 2). As a countermeasure against this problem, it has been practiced to vary the amount of silicon brought into reaction with nickel depending respectively on the N type and the P type, i.e., to vary the initial amount of silicon to be brought into reaction depending respectively on the N type and the P type.
The full-silicide gate structure in the related art is generally produced by a process in which gate electrode surface layers are exposed by the CMP (Chemical Mechanical Polishing) technique, followed by silicidation reactions (refer to, for example, Japanese Patent Laid-open No. 2006-140319, hereinafter referred to as Patent Document 1, FIG. 9). An example has been known in which the problem arising from volume expansion is suppressed by controlling the initial amounts of gate silicon at the time of conducting silicidation reactions respectively for the N-type FET and the P-type FET after the gate electrode surface layers are exposed by CMP (refer to, for example, Non-Patent Document 2).
However, the technology in which etch-back is carried out after the respective gate electrode heights of the N-type FET and the P-type FET are controlled would disadvantageously lead to dispersions of electrical characteristics through dispersion of in-plane evenness in the RIE (Reactive Ion Etching) process.
In view of this, a method in which the initial poly-silicon amounts are controlled taking into account the volume expansion in the gate silicidation reactions has been improved by control of gate heights and gate shapes, and, as a related art, a structure has been known in which the upper ends of gates are rounded (refer to, for example, FIG. 9 of Japanese Patent Laid-open No. 2006-32410, hereinafter referred to as Patent Document 2, and FIG. 1 of Japanese Patent Laid-open No. 2003-224265, hereinafter referred to as Patent Document 3).
Besides, as a method in which other factor than gate height is controlled, there is a method in which the gate shape is controlled to be a tapered shape for the purpose of reducing the volume expansion of the gate of the P-type FET. However, if the N-type gate is simultaneously provided with the same shape as the P-type gate in this method, the volume expansion of the N-type gate is insufficient, so that the stress exerted on the channel part is reduced and the ON current cannot be increased.